1. Field of the Invention
The present invention relates to the process of bridging a video signal from one format to another; and more particularly to processes and structures used in integrated circuits provided for that purpose.
2. Description of Related Art
There is an on-going transition from raster-scan CRT display devices to pixel-based displays, like liquid crystal display LCD monitors, plasma TVs and projection TVs. Pixel-based display devices have strict timing specifications, typically stricter then the typical cathode ray tubes CRT's used in standard televisions and computer monitors.
Conditions that must be met for successful bridging include the forcing of the input frame rate iFR to match the output frame rate oFR, and that the buffer used during the bridging not be subject to overflow or underflow conditions. Further it is desirable that the buffer used for bridging be small as possible to save each chip area and implementation costs. Finally, the parameters for the output video stream must conform to the physical limitations of the output display device, which will have minimum and maximum values as outlined above. The following parameters are involved in bridging the formats.                Fid—the frequency of the pixel clock for the input video stream.        iV—the number of input lines        iVDE—the number of displayed input lines        iH—the number of input pixels per line        iHDE—the number of displayed input pixels per line        iFR—the input frame rate        Fod—the frequency of the pixel clock for the output video stream.        oV—the number of output lines        oVDE—the number of displayed output lines        oH—the number of output pixels per line        oHDE—the number of displayed output pixels per line.        oFR—the output frame rate.        
Min/max Fpd—the specified range of frequencies of the pixel clock for the output video device.
Min/max pV—the specified range for the number of output lines for the output device
Min/max pVDE—the specified range for the number of displayed output lines for the output device
Min/max pH—the specified range for the number of output pixels per line for the output device
Min/max pHDE—the specified range for the number of displayed output pixels per line for the output device
Min/max pFR—the specified range for the output frame rate for the output device.
Difficulties in bridging the formats arise because of non-integer ratios of the input frame size to the output frame size, as expressed for example in the parameters iV, iVDE, iH and iHDE, for the input video stream and oV, oVDE, oH and oHDE for the output video stream. The difficulties are aggravated by the limitations of matching input and output clock rates used for the bridging.
Prior art techniques for managing the problems that arise because of the finite precision for generation of the output clock Fod and/or the use of spread-spectrum effects for the pixel clocks involve using a larger frame or line buffer. However, such buffers are a typically implemented using SRAM or SDRAM memory to accommodate the speed differences and variations. Because SRAM and SDRAM memory is expensive to implement, it is desirable to keep the buffer a small as possible.
In order to keep the buffer small while preventing overflow or underflow, the system must maintain the distance between input and output active pixel streams constant within a small range. Thus the system must tend to keep the elapsed time for the input active pixels equal to the elapsed time for the output active pixels.
Consider the following equations:iH*iVDE*(1/Fid)=oH*oVDE*(1/Fod)  eq-1Fod=(oH*oVDE*Fid)/(iH*iVDE)  eq-2, derived from eq-1oH=(iH*iVDE*Fod)/(oVDE*Fid)  eq-3, derived from eq-1
Equation 1 illustrates the relation that results from a requirement that the buffer not overflow or underflow during active lines in a frame. That is the number of pixels per line on the input iH times the number of active lines on the input iVDE (input lines during which display enable is asserted) divided by the frequency of input clock Fid, should be equal to the number of pixels per line on the output oH times the number of active lines on the output oVDE (output lines during which display enable is asserted) divided by the frequency the output clock Fod. Equation 2 illustrates a computation of the frequency the output clock required to achieve the relation of equation 1. Equation 3 illustrates a computation of the number of pixels in the output lines that is needed to achieve the relation of equation 1.
For a typical video scaling bridge, the processor waits for the input video stream to fill two active scan lines into line buffers before the output stream begins unloading output active pixels. Thus, a minimum of two lines of memory is required for the line buffer in a typical system.
However, the output clock frequency Fod cannot be precisely controlled. It is generated by a clock source that translates a reference clock to the output clock frequency Fod, using a frequency divider or other component having a finite precision. In some embodiments, the output clock frequency Fod is intentionally dithered to induce so-called spread spectrum effects that reduce electromagnetic interference. Therefore, it can be seen from equations that the value of oH cannot be precisely controlled.
Consider an example in which iH is 1040, iV is 660, iHDE is 800, iVDE is 600, and the frequency of input clock is 50 MHz, while the desired output parameters include oH of 1316, oV of 1120, oHDE of 1280, oVDE of 1024, and the frequency of the output clock of about 108 MHz. In one embodiment the actual frequency of the output clock Fod is produced using a crystal oscillator reference clock of 14.318 MHz, and using a frequency divider having a value for example of 15/2. Therefore we have:Fod=15/2*14.318 MHz=107.385 MHz
Applying equation 3, we have the number of pixels per line oH at this Fod, as follows:oH=(1040*600*107.385)/(1024*50)=1308.755
This suggests that the output number of pixels per line oH should be 1309, which differs from the ideal of 1316. Given 1024 active output lines, and a requirement that the input frame rates match, we can compute the number of extra lines needed in the buffer for compensating the speed difference as follows:1024*(1−(actual-Fod*1316)/(ideal-Fod*1309))=0.2  eq-4
Thus, in this example, the line buffer needs to be extended by 0.2 lines to accommodate the actual output frequency. If one or both of the input pixel clock Fid or the output pixel clock Fod is not constant, but is dithered, for example, with a range is of 0.5 to 1.0 percent variation to reduce electromagnetic interference effects, then the buffer needs to be further increased in size. In a worst-case where both clocks are dithered by one percent, then two percent of the number of active lines the output device oVDE need to be provided in the buffer for the purposes of accommodating these variations. Thus, for our example in which there are 1024 active output lines, an additional 20.48 lines of buffer memory would be required. Such an additional buffer would take a huge amount of area on the bridge chip, and make it much more expensive.
Also the requirement that input frame rate iFR equal output frame rate oFR, which means input frame period=output frame period, including both inactive and active lines, yields the following equations:iH*iV*(1/Fid)=oH*oV*(1/Fod)  eq-5oV=(iH*iV*Fod)/(oH*Fid)  eq-6
As can be seen from equation 6, the number of output scan lines in a frame may be not an integer number, resulting in a residue scan line that may be too short for the destination display device.
Taking for example the Sharp SXGA LCD panel as the output display device, we compute the bridging parameters in two steps:
Step 1: In order to prevent overflow/underflow for bridge within a line buffer, we should choose:                desired Fod=(1024*1316*50 MHz)/(600*1040)=107.9795 . . . MHz        
However, we have no infinitely precise Fod clock generator, thus                Actual Fod=15/2*14.318 MHz=107.385 MHz        Adjusted oH=1309        
Step 2: In order to meet iFR=oFR, the ideal number of output scan lines is as follows:Ideal oV=(107.385 MHz*1040*660)/(50 MHz*1309)=1126.189 lines  eq-7
Thus, the residue width is 0.189 line, which means that the residue line has:0.189*1309˜=247 pixels  eq-8
This 247 pixel width violates the minimum line width limitation of display device, in which the minimum line width is 648 clocks*2=1296 pixels. Thus, the overall system can not meet the three requirements (1) that the line buffer not overflow/underflow, (2) that the frame rate of the input match the frame rate of the output, and (3) that the residue line not be smaller than the device minimum.
Taking for another example, the Fujitsu PDP as the physical display device, we determine the bridging parameters as follows:
Step 1: Compute output pixel clock frequency as follows, selecting 1080 pixels per scan line and around 600 lines per frame:
Desired Fod=1080*600*72/2=23.328 MHz (divided by 2 is because 2 pixels per clock)                Actual Fod=13/8 *14.318 MHz=23.267 MHz        
Step 2: In order to meet iFR=oFR, the ideal number of output scan lines is                oV=(23.267 MHz*2*1040*660)/(50 MHz*1080)=591.49 lines        
The residue line width in time, is                0.49*(1080/2)/23.267=11.37 μsec<22.7 μsec,        where 22.7 μsec is the minimum acceptable line width for the display device.        
The residue line calculation can get even worse if the input pixel clock Fid is less constant, such as clocks from a VHS-player or broadcast TV/HDTV. In these cases, the width of residue line is unstable due to an unstable Fid.
Thus, the prior art systems generate residue lines with either a fixed or variable width. If the number of output lines oV derived from the input video stream, given the precision of the output clock, is not an integer, a residue line of roughly fixed width is generated from video sources like a VGA formatted video stream with a relatively stable input pixel clock Fid. The derived number of output lines oV can vary, ranging for example from 1000.3 to 1001.6 if the speed of input pixel stream has significant fluctuation. For example, VHS player, broadcast TV or high-definition TV HDTV formatted streams may have pixel clocks which fluctuate. The residue line problem is worse where the destination device is unable to handle lines that are less than a minimum specified parameter.
Another problem which occurs in the prior art arises from the fact that the actual output frequency for the display Fod will fluctuate simply because of the short-term variation of the clock generator. For example, a typical phase locked loop clock generator may fluctuate plus or minus 0.5 percent over relatively short terms. Prior art systems address this problem by increasing the size of the line buffers, increasing chip cost.
Furthermore, in the scaling of the input video frame to the output video frame, the number of output lines oV or the number of output pixels per line oH may be required to exceed the maximum number specified for the output device. Thus, as derived above in equation 7, the number of output lines oV for the Sharp TFT LCD device was determined to be 1126. However, the maximum number of lines allowed on the device is 1080. This causes unstable display output.
It can be seen that the problem of bridging an input video format to an output video format in an economical manner which provides stable display output for a range of output devices is complex. As the number of types of output device increases, the problem is becoming more prevalent. It is desirable therefore to provide techniques adaptable to integrated circuit implementations for bridging video formats.